Built-in current sensor for ΔI/sub DDQ/ testing

Built-in current sensor for IDDQ testing

This paper presents the implementation of a built-in current sensor for DDQ testing. In contrast to conventional built-in current monitors, this implementation has three distinctive features: 1) built-in self-calibration to the process corner in which the circuit under test was fabricated; 2) digital encoding of the quiescent current of the circuit under test for robustness purposes; and 3) ena...

A practical built-in current sensor for I_DDQ testing

Fuzzy-based CMOS circuit partitioning in built-in current testing

We propose a fuzzy-based approach which provides a soft threshold to determine the module size for CMOS circuit partitioning in built-in current testing (BICT). Experimental results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning in comparison with other approaches with a fixed threshold, and a better module size can thus be determin...

Fuzzy-based circuit partitioning in built-in current testing

Partitioning a digital circuit into modules before implementing on a single chip is key to balancing between test cost and test correctness of built-in current testing (BICT). Most partitioning methods use statistic analysis to find the threshold value and then to determine the size of a module. These methods are rigid and inflexible since IDDQ testing requires the measurement of an analog quan...

Power Supply Partitioning for Placement of Built-in Current Sensors for Iddq Testing

Power Supply Partitioning for Placement of Built-In Current Sensors for IDDQ Testing. (December 2003) Abhijit Prasad, B.E., Regional Engineering College, Trichy, India Chair of Advisory Committee: Dr. Duncan Moore Henry Walker IDDQ testing has been a very useful test screen for CMOS circuits. However, with each technology node the background leakage of chips is rapidly increasing. As a result i...